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1 motorola tmos power mosfet transistor device data
? ? nchannel enhancementmode silicon gate this a dvance d t mo s e fet i s d esigne d t o w ithstan d h igh energy in the avalanche and commutation modes. the new energy efficient d esig n a ls o o ffer s a d raintosourc e d iode w it h a f ast recovery t ime . d esigne d f o r l o w v oltage , h ig h s pee d s witching application s i n p owe r s upplies , c onverter s a n d p w m m otor controls, these devices are particularly well suited for bridge circuits where d iod e s pee d a n d c ommutatin g s af e o peratin g a rea s a re critical a n d o ffe r a dditiona l s afet y m argi n a gainst u nexpected voltage transients. ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drainsource voltage v dss 100 vdc draingate voltage (r gs = 1.0 m w ) v dgr 100 vdc gatesource e continuous e nonrepetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain voltage e continuous e continuous @ 100 c e single pulse (t p 10 m s) i d i d i dm 33 20 99 adc apk total power dissipation derate above 25 c p d 125 1.0 watts w/ c operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy e starting t j = 25 c (v dd = 25 vdc, v gs = 10 vdc, i l = 33 apk, l = 1.000 mh, r g = 25 w ) e as 545 mj thermal resistance e junction to case e junction to ambient r q jc r q ja 1.00 62.5 c/w maximum lead t emperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c designer's data for aw orst caseo conditions e the designer ' s data sheet permits the design of most circuits entirely from the information presented. soa limit curves e representing boundaries on device characteristics e are given to facilitate aworst caseo design. efet and designer' s are trademarks of motorola, inc. tmos is a registered trademark of motorola, inc. preferred devices are motorola recommended choices for future use and best overall value. rev 3 order this document by mTP33N10E/d
semiconductor technical data ? motorola, inc. 1995 tmos power fet 33 amperes 100 volts r ds(on) = 0.06 ohm motorola preferred device ? d s g case 221a06, style 5 to220ab
2 motorola tmos power mosfet transistor device data electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drainsource breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 100 e e 118 e e vdc mv/ c zero gate voltage drain current (v ds = 100 vdc, v gs = 0 vdc) (v ds = 100 vdc, v gs = 0 vdc, t j = 25 c) i dss e e e e 10 100 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss e e 100 nadc on characteristics (1) gate threshold voltage (v ds = v gs , i d = 250 m adc) temperature coefficient (negative) v gs(th) 2.0 e e 7.0 4.0 e vdc mv/ c static drainsource onresistance (v gs = 10 vdc, i d = 16.5 adc) r ds(on) e 0.04 0.06 ohm drainsource onvoltage (v gs = 10 vdc) (i d = 33 adc) (i d = 16.5 adc, t j = 25 c) v ds(on) e e 1.6 e 2.4 2.1 vdc forward transconductance (v ds = 8.0 vdc, i d = 16.5 adc) g fs 8.0 e e mhos dynamic characteristics input capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c iss e 1830 2500 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz) c oss e 678 1200 reverse transfer capacitance f = 1.0 mhz) c rss e 559 1100 switching characteristics (2) turnon delay time (v dd = 50 vdc, i d = 33 adc, v gs = 10 vdc, r g = 9.1 w ) t d(on) e 18 40 ns rise time (v dd = 50 vdc, i d = 33 adc, v gs = 10 vdc, r g = 9.1 w ) t r e 164 330 turnoff delay time v gs = 10 vdc, r g = 9.1 w ) t d(off) e 48 100 fall time g = 9.1 w ) t f e 83 170 gate charge (see figure 8) (v ds = 80 vdc, i d = 33 adc, v gs = 10 vdc) q t e 52 110 nc (see figure 8) (v ds = 80 vdc, i d = 33 adc, v gs = 10 vdc) q 1 e 12 e (v ds = 80 vdc, i d = 33 adc, v gs = 10 vdc) q 2 e 32 e q 3 e 24 e sourcedrain diode characteristics forward onvoltage (1) (i s = 33 adc, v gs = 0 vdc) (i s = 33 adc, v gs = 0 vdc, t j = 125 c) v sd e e 1.0 0.98 2.0 e vdc reverse recovery time (see figure 14) (i s = 33 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t rr e 144 e ns (see figure 14) (i s = 33 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t a e 108 e (i s = 33 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t b e 36 e reverse recovery stored charge q rr e 0.93 e m c internal package inductance internal drain inductance (measured from contact screw on tab to center of die) (measured from the drain lead 0.25 from package to center of die) l d e 3.5 4.5 e nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s e 7.5 e nh (1) pulse test: pulse width 300 m s, duty cycle 2%. (2) switching characteristics are independent of operating junction temperature.
3 motorola tmos power mosfet transistor device data typical electrical characteristics 5.5 r ds(on) , draint osource resist ance (normalized) r ds(on) , draint osource resist ance (ohms) r ds(on) , draint osource resist ance (ohms) 0 2 4 6 8 10 0 30 50 60 90 v ds , draintosource voltage (volts) figure 1. onregion characteristics i d , drain current (amps) i d , drain current (amps) v gs , gatetosource voltage (volts) figure 2. transfer characteristics 0 12 24 36 48 60 0.02 0.03 0.05 0.07 0.09 5 17 29 47 59 65 0.037 0.041 0.045 0.049 0.053 i d , drain current (amps) figure 3. onresistance versus drain current and temperature i d , drain current (amps) figure 4. onresistance versus drain current and gate voltage 50 0.6 0.8 1.2 1.6 2.0 20 40 60 80 90 100 10 100 1000 10000 t j , junction temperature ( c) figure 5. onresistance variation with temperature v ds , draintosource voltage (volts) figure 6. draintosource leakage current versus voltage i dss , leakage (na) 25 0 25 50 75 100 125 150 t j = 25 c v ds 10 v t j = 55 c 25 c 100 c t j = 100 c 25 c 55 c t j = 25 c v gs = 0 v v gs = 10 v 80 70 20 40 1 3 5 7 9 10 9 v 5 v 6 v 7 v 8 v v gs = 10 v 0 30 50 60 90 80 70 20 40 10 2.0 3.0 4.0 5.0 6.0 7.0 2.5 3.5 4.5 6.5 7.5 8.5 9.5 8.0 9.0 10 0.08 0.06 0.04 6 18 30 42 54 66 0.051 0.047 0.043 0.039 11 23 35 53 41 1.0 1.4 1.8 30 50 70 t j = 125 c 25 c 100 c v gs = 10 v 15 v v gs = 10 v i d = 16.5 a
4 motorola tmos power mosfet transistor device data power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the l ength s o f v ariou s s witchin g i nterval s ( d t ) a r e d eter- mined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is dif ficult to use for calculat - ing r is e a nd f al l b ecaus e d raingat e c apacitanc e v aries greatly with applied voltage. accordingly , gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resis - tive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnof f delay times, gate current is not constant. the simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the of fstate condition when cal - culating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements com - plicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a func- tion of drain current, the mathematical solution is complex. the m osfe t o utpu t c apacitanc e a ls o c omplicate s t he mathematics. and finally, mosfets have finite internal gate resistance w hic h e ffectivel y a dd s t o t he r esistanc e o f t he driving source, but the internal resistance is dif ficult to mea - sure and, consequently, is not specified. the resistive switching time variation versus gate resis - tance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfet s may be safely op - erated i nt o a n i nductiv e l oad ; h owever , s nubbin g r educes switching losses. 10 0 10 15 20 25 gatetosource or draintosource voltage (volts) c, cap acitance (pf) figure 7. capacitance variation 5000 4500 4000 3500 2500 1500 500 0 v gs v ds t j = 25 c v ds = 0 v v gs = 0 v 3000 2000 1000 5 5 c iss c oss c iss c rss c rss
5 motorola tmos power mosfet transistor device data draintosource diode characteristics 0.5 0.6 0.7 0.8 0.9 1.05 0 12 21 27 33 v sd , sourcetodrain voltage (volts) figure 8. gatetosource and draintosource voltage versus total charge i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 10 t, time (ns) t r t f t d(off) t d(on) v gs = 0 v t j = 25 c figure 10. diode forward voltage versus current 140 v gs , ga tetosource vol tage (vol ts) 120 100 80 60 40 20 0 12 8 4 0 q g , total gate charge (nc) v ds , draint osource vol tage (vol ts) 14 10 6 2 10 20 30 40 60 t j = 25 c i d = 33 a v ds v gs 50 0 q1 q2 qt q3 100 30 24 18 6 9 15 3 0.55 0.65 0.75 0.85 0.95 1.0 v dd = 50 v i d = 33 a v gs = 10 v t j = 25 c safe operating area the forward biased safe operating area curves define the m aximu m s imultaneou s d raintosourc e v oltage a nd drain current that a transistor can handle safely when it is for - ward biased. curves are based upon maximum peak junc - tion temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistancegeneral data and its use.o switching between the of fstate and the onstate may tra - verse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power aver - aged o ve r a c omplet e s witchin g c ycl e m us t n o t e xceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reli - able operation, the stored energy from circuit inductance dis - sipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions dif fering from those specified. although industry practice is to rate in terms of energy , avalanche energy capability is not a con - stant. the energy rating decreases nonlinearly with an in - crease o f p ea k c urrent i n a valanch e a n d p ea k j unction temperature. although many efets can withstand the stress of drain tosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous cur- rent (i d ), in accordance with industry custom. the energy rat - ing m us t b e d erate d f o r t emperatur e a s s how n i n t he accompanying graph (figure 12). maximum energy at cur - rents below rated continuous i d can safely be assumed to equal the values indicated.
6 motorola tmos power mosfet transistor device data safe operating area t j , starting junction temperature ( c) e as , single pulse draint osource figure 11. maximum rated forward biased safe operating area 0.1 1.0 100 v ds , draintosource voltage (volts) figure 12. maximum avalanche energy versus starting junction temperature 0.1 10 1000 avalanche energy (mj) i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 0 25 50 75 100 125 500 300 200 100 i d = 33 a 400 100 1.0 10 150 t, time (ms) figure 13. thermal response r(t), normalized effective transient thermal resist ance r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b v gs = 20 v single pulse t c = 25 c 0.2 0.1 0.05 0.02 0.01 single pulse d = 0.5 50 550 350 250 150 450 1.0e05 1.0e04 1.0e02 0.1 1.0 0.01 1.0e03 1.0e01 1.0e+01 1.0e+00 100 m s 1 ms 10 ms dc
7 motorola tmos power mosfet transistor device data package dimensions case 221a06 issue y notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 1.15 z 0.080 2.04 b q h z l v g n a k f 1 2 3 4 d seating plane t c s t u r j style 5: pin 1. gate 2. drain 3. source 4. drain
8 motorola tmos power mosfet transistor device data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . literature distribution centers: usa: motorola literature distribution; p .o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature centre; 88 t anners drive, blakelands, milton keynes, mk14 5bp , england. jap an: nippon motorola ltd.; 4321, nishigotanda, shinagawaku, t okyo 141, japan. asia p acific: motorola semiconductors h.k. ltd.; silicon harbour center , no. 2 dai king street, t ai po industrial estate, t ai po, n.t., hong kong. mTP33N10E/d
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